A DVFS based HEVC decoder for energy-efficient software implementation on embedded processors

Erwan Nogues 1 Berrada Romain 1 Maxime Pelcat 1 Daniel Menard 1 Erwan Raffin 1
1 IETR - Institut d'Electronique et de Télécommunications de Rennes
Abstract : Software video decoders for mobile devices are now a reality thanks to recent advances in Systems-on-Chip (SoC). The challenge has now moved to designing energy efficient systems. In this paper, we propose a light Dynamic Voltage Frequency Scaling (DVFS)-enabled software adapted to the much varying processing load of High Efficiency Video Coding (HEVC) real-time decoding. We analyze a practical evaluation of a HEVC decoder using our proposal on a Samsung Exynos low-power SoC widely used in portable devices. Experimental results show more than 50% of power savings on a real-time decoding when compared to the same software managed by the OnDemand Linux power management. For mobile applications, the proposed method can achieve 720p video HEVC decoding at 60 frames per second consuming approximately 1.1W with pure software decoding on a general purpose processor.
Keywords : HEVC decoder DVFS Energy low power
Document type :
Conference papers
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https://hal-insa-rennes.archives-ouvertes.fr/hal-01184630
Contributor : Erwan Nogues <>
Submitted on : Monday, August 17, 2015 - 10:07:00 AM
Last modification on : Tuesday, February 5, 2019 - 3:58:22 PM

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INSA-RENNES | UNIV-RENNES1 | IETR | UNIV-NANTES | IETR-INSA | UR1-UFR-ISTIC | IETR-VAADER | UNIV-RENNES | INSA-GROUPE

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Erwan Nogues, Berrada Romain, Maxime Pelcat, Daniel Menard, Erwan Raffin. A DVFS based HEVC decoder for energy-efficient software implementation on embedded processors. IEEE International Conference on Multimedia and Expo (ICME), Jun 2015, Torino, Italy. ⟨10.1109/ICME.2015.7177406⟩. ⟨hal-01184630⟩

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